// See LICENSE for license details.

#ifndef _EVALSOC_UART_H
#define _EVALSOC_UART_H

#ifdef __cplusplus
extern "C" {
#endif

/* Register offsets */
#define UART_REG_TXFIFO         0x00
#define UART_REG_RXFIFO         0x04
#define UART_REG_TXCTRL         0x08
#define UART_REG_RXCTRL         0x0c
#define UART_REG_IE             0x10
#define UART_REG_IP             0x14
#define UART_REG_DIV            0x18

/* TXCTRL register */
#define UART_TXEN               0x1
#define UART_TXWM(x)            (((x) & 0xffff) << 16)

/* RXCTRL register */
#define UART_RXEN               0x1
#define UART_RXWM(x)            (((x) & 0xffff) << 16)

/* IP register */
#define UART_IP_TXWM            0x1
#define UART_IP_RXWM            0x2

#define UART_TXFIFO_FULL        (1<<31)
#define UART_RXFIFO_EMPTY       (1<<31)

#define UART_TXCTRL_TXCNT_OFS   (16)
#define UART_TXCTRL_TXCNT_MASK  (0x1F << UART_TXCTRL_TXCNT_OFS)
#define UART_TXCTRL_TXEN_OFS    (0)
#define UART_TXCTRL_TXEN_MASK   (0x1 << UART_TXCTRL_TXEN_OFS)
#define UART_TXCTRL_NSTOP_OFS   (1)
#define UART_TXCTRL_NSTOP_MASK  (0x3 << UART_TXCTRL_NSTOP_OFS)

#define UART_RXCTRL_RXCNT_OFS   (16)
#define UART_RXCTRL_RXCNT_MASK  (0x1F << UART_RXCTRL_RXCNT_OFS)
#define UART_RXCTRL_RXEN_OFS    (0)
#define UART_RXCTRL_RXEN_MASK   (0x1 << UART_RXCTRL_RXEN_OFS)

#define UART_IE_TXIE_OFS        (0)
#define UART_IE_TXIE_MASK       (0x1 << UART_IE_TXIE_OFS)
#define UART_IE_RXIE_OFS        (1)
#define UART_IE_RXIE_MASK       (0x1 << UART_IE_RXIE_OFS)

#define UART_IP_TXIP_OFS        (0)
#define UART_IP_TXIP_MASK       (0x1 << UART_IP_TXIP_OFS)
#define UART_IP_RXIP_OFS        (1)
#define UART_IP_RXIP_MASK       (0x1 << UART_IP_RXIP_OFS)

//Loopback mode
#define Loopback_Mode_Disable      0x0  //disable loopback mode
#define Loopback_Mode_Enable       0x10 //enable loopback mode

// RCVR_Trigger:
#define RCVR_Trigger_CHAR_1         0x0 // 1 character
#define RCVR_Trigger_QUARTER_FULL   0x1<<6 // 1/4 full
#define RCVR_Trigger_HALF_FULL      0x2<<6 // 1/2 full
#define RCVR_Trigger_FULL_2         0x3<<6 // 2 less than full

typedef enum{
    DATA_BITS_5 =0x5,
    DATA_BITS_6,
    DATA_BITS_7,
    DATA_BITS_8
}data_bits_t;

typedef enum{
    PARITY_NONE,
    PARITY_ODD, //奇数校验
    PARITY_EVEN //偶数校验
}parity_t;

typedef enum{
    STOP_BITS_1,
    STOP_BITS_1_5,
    STOP_BITS_2
}stop_bits_t;



int32_t uart_init( dw_uart_regs_t * puart,uint32_t baudrate,uint32_t Loopback_Mode,uint32_t RCVR_Trigger,data_bits_t data_bits,stop_bits_t stop_bits,parity_t parity);
int32_t uart_write( dw_uart_regs_t * puart, uint8_t val );
uint8_t uart_read( dw_uart_regs_t * puart );
int dbg_test_dma_uart_rx(dw_uart_regs_t * puart,uint32_t uart_base,uint32_t channer,uint32_t dma_rx_req,uint32_t Memory_addr,uint32_t len);
int dbg_test_dma_uart_tx(dw_uart_regs_t * puart,uint32_t uart_base,uint32_t channer,uint32_t dma_tx_req,uint32_t Memory_addr,uint32_t len);
void dma_uart0_case( void );
void dma_uart1_case( void );

#if 0
int32_t uart_config_stopbit(UART_TypeDef* uart, UART_STOP_BIT stopbit);
int32_t uart_set_tx_watermark(UART_TypeDef* uart, uint32_t watermark);
int32_t uart_enable_txint(UART_TypeDef* uart);
int32_t uart_disable_txint(UART_TypeDef* uart);
int32_t uart_set_rx_watermark(UART_TypeDef* uart, uint32_t watermark);
int32_t uart_enable_rxint(UART_TypeDef* uart);
int32_t uart_disable_rxint(UART_TypeDef* uart);
int32_t uart_get_status(UART_TypeDef* uart);
int32_t uart_clear_status(UART_TypeDef* uart, uint32_t mask);
#endif

#ifdef __cplusplus
}
#endif
#endif 
